As modern signaling systems progress deeper into the gigahertz range, sources of previously-tolerable signal skew begin to present substantial sources of timing error. For example, in modern memory systems, source synchronous timing signals (strobe signals or clock signals) are often transmitted alongside corresponding groups of data signals, eight or sixteen data signals, for example, and used to control the data sampling time. By designing the signal transmission paths so that the timing signal and data signals experience similar propagation delays, the phase relationship established between the timing signal and data signals at the transmitting device may be maintained upon arrival of those signals at the receiving device. Despite this effort, fan-out differences between the timing and data signals at the receiving device (the timing signal is typically provided to sampling inputs of multiple receivers, while the data signal is provided to a single receiver input) yield different loading characteristics for the timing and data signal paths and thus produce skew between timing signal transitions and the desired data signal sampling point. Signal line loading may be equalized by providing a clock tree in the timing signal path (which also serves to meet the required clock fan-out), but the intrinsic delay of the clock tree itself presents a source of voltage and temperature dependent timing skew that generally requires active compensation.
FIG. 1A illustrates a prior-art memory system having a memory controller 101 to transmit strobe, data and clock signals to a memory device 103, which itself includes circuitry to adjust the phase of the incoming strobe signal (timing signal) as necessary to compensate for a voltage and temperature dependent delay in a clock tree. As shown, a transmit clock (tClk) is supplied to a set of n data drivers 105 which output an n-bit data word via data lines DQ0-DQn−1. The transmit clock is also supplied, via a quadrature delay element 107 (90° delay element) to a data strobe driver 109, which transmits a strobe signal via data strobe path DQS to the memory device. In the system shown, data is transmitted in response to each edge of the transmit clock signal, rising and falling, so that two bits are transmitted per tClk cycle. Accordingly, the quadrature delay element delays the data strobe signal by a half-bit time (one fourth of a tClk cycle or 90°) thus aligning the data strobe edge nominally with the center of the data eye (i.e., data valid interval) as shown in FIG. 1B.
Within memory device 103, the data strobe signal is supplied to a clock tree 115 which, in turn, replicates the data strobe in the form of multiple same-phase sampling signals (s0-sn−1) which are phase-delayed relative to the data strobe signal as shown in FIG. 1B according to the clock tree propagation delay. As shown, the sampling signals are supplied to respective receive circuits 117 to control the data sampling point for data signals arriving via data lines DQ0-DQn−1.
Because the clock tree propagation delay tends to be voltage and temperature dependent, an active locked-loop circuit 119 (e.g., delay-locked loop (DLL) or phase-locked loop (PLL)) is typically provided within the memory device and used to establish an actively-controlled propagation delay (i.e., by generating control signal, “ctrl”) through a variable delay element 121 provided in the data strobe path. For example, the locked-loop circuit 119 may include a replica of the clock tree circuit 115 and variable delay element 121 within the loop feedback path so that the combined propagation delay of the clock tree circuit and delay element is adjusted, by the negative feedback loop, to match a bit time of the transmit clock (tClk cycle/2), thereby shifting the sampling signals (s0-sn−1) forward by the bit time less the clock tree propagation delay and thus establishing the sampling signal edge at a desired alignment with the data eyes of the incoming data signals. This phase adjusted signal is shown in FIG. 1B as signal s0′ with delay equal to a bit time (BT) less clock tree delay (CDT).
In a typical implementation, a free-running master clock signal (mClk, which is usually mesochronously related to the transmit clock signal) is provided to the memory device 103 to establish a timing reference for the locked loop circuit 119. Consequently, though the arrangement of FIG. 1A is generally effective for deskewing the sampling signals, the presence of a continuously clocked circuit within the memory device results in considerable power consumption and heat generation; power loss and heating that is multiplied by the numerous memory devices typically included in a memory system.